Maximal tile generation technique and associated methods for designing and manufacturing VLSI circuits

摘要

A non-maximal arrangement of component tiles is reconfigured into a maximal arrangement. For each identified active segment of a first span not having a matching active segment in a second span, a maximal component tile having a width generally equal to the width of the identified active segment of the first span and a height generally equal to the distance separating the first and second spans is generated. The first span is then modified by deleting the matching active segment of the first span while adding each unmatched active segment of the second span. Maximal space tiles are generated from inactive segments of the spans using a similar process. The process is then repeated for each unselected span which fails to match the modified first span.