发明名称 |
Semiconductor device and semiconductor memory using the same |
摘要 |
A cell transistor includes source/drain regions formed at a lower level than part of its channel region. A select transistor has a channel region and source/drain regions formed at substantially the same level as the source/drain regions of the cell transistor. One of the source/drain regions of the cell transistor and one of the source/drain regions of the select transistor are electrically interconnected to each other in substantially the same plane.
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申请公布号 |
US2003183872(A1) |
申请公布日期 |
2003.10.02 |
申请号 |
US20030397377 |
申请日期 |
2003.03.27 |
申请人 |
MIIDA TAKASHI |
发明人 |
MIIDA TAKASHI |
分类号 |
G11C16/04;G11C16/02;G11C16/06;H01L21/8238;H01L21/8247;H01L27/092;H01L27/10;H01L27/105;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L29/788;H01L29/76;H01L29/94 |
主分类号 |
G11C16/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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