TIMING MEASUREMENT SYSTEM AND METHOD USING A COMPONENT-INVARIANT VERNIER DELAY LINE

摘要

In recent years, much effort has been placed on improving the performance of timing and jitter measurement devices using Delay Locked Loop (DLL) and Vernier Delay Line (VDL) techniques. However, these approaches require highly matched elements in order to reduce differential non linearity timing errors. In an attempt to reduce the requirement on element matching, a component invariant VDL technique is disclosed that enables the measurement device to be synthesized from an RTL description. The present invention is based on a single stage VDL structure, which is used to mimic the behavior of a complete VDL. Furthermore, as test time is an important consideration during a production test, a method and system is provided that reduces test time at the expense of additional hardware.