发明名称 Memory architecture and its method of operation
摘要 A data storage comprises memory having a plurality of memory cells operative to retain data until read. A buffer cooperates, under the control of an address and buffer manager, with the memory to receive data read from the memory cells of a plurality of memory blocks of the memory. Error correction logic is operatively configured to examine the data read from the memory blocks and determine and correct corrupt data thereof. After the data has been processed by the error correction logic, the address and buffer manager enables write circuitry to write-back the select blocks of memory cells with the processed data of the buffer.
申请公布号 US2003188251(A1) 申请公布日期 2003.10.02
申请号 US20020112835 申请日期 2002.03.27
申请人 BROWN MICHAEL A.;COULSON RICHARD L. 发明人 BROWN MICHAEL A.;COULSON RICHARD L.
分类号 G06F11/10;G11C7/10;G11C11/22;(IPC1-7):G11C29/00 主分类号 G06F11/10
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