发明名称 |
Methods for forming metal interconnections for semiconductor devices having multiple metal depositions |
摘要 |
Methods of forming an integrated circuit device can include forming an interlevel dielectric film on an integrated circuit substrate including a conductive portion thereof. The interlevel dielectric film includes a contact hole therein exposing a portion of the conductive portion of the integrated circuit substrate, and the dielectric film includes a trench therein communicating with the contact hole wherein the trench is in a surface of the interlevel dielectric film opposite the integrated circuit substrate. A first metal layer is formed in the contact hole preferentially with respect to formation of the first metal layer on a surface of the interlevel dielectric film opposite the integrated circuit substrate. After preferentially forming the first metal layer in the contact hole, a second metal layer is formed on the surface of the interlevel dielectric film opposite the integrated circuit substrate.
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申请公布号 |
US2003186539(A1) |
申请公布日期 |
2003.10.02 |
申请号 |
US20030353386 |
申请日期 |
2003.01.28 |
申请人 |
LEE JONG-MYEONG;LEE HYEON-DEOK;PARK IN-SUN;LEE JU-BUM |
发明人 |
LEE JONG-MYEONG;LEE HYEON-DEOK;PARK IN-SUN;LEE JU-BUM |
分类号 |
H01L21/3205;H01L21/768;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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