| 摘要 |
A method and apparatus for detecting and decomposing component loops in a logic design is described. The invention first detects any component loops when the compiler schedules the processing order of the combinational logic components in the digital circuit design. To identify component loops, the compiler levelizes the design and sorts the combinational logic components, making sure that no true combinational logic loops exist. If the sorting fails, a component loop exists, and the compiler identifies such components and selects one or more of the components to be split. Next, the invention corrects the component loops by splitting a component into multiple sub-components. By splitting a component into multiple sub-components, the output of the split component no longer provides input to another component, and hence, the component loop is broken. In this way, the compiler is able to generate executable code configured to run in a cycle-based simulation system or in a general purpose computing environment, by avoiding false component loops.
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