| 摘要 |
<p>PROBLEM TO BE SOLVED: To realize a semiconductor component element which can be easily manufactured by the existing process and has a multi-level interconnection not needing a large line width near via holes. SOLUTION: The method of manufacturing a semiconductor component element having a multi-level interconnection comprises a step of manufacturing a device 12 on a substrate 11, a step of forming an interconnection layer 15 on the substrate 11, a step of depositing a dielectric layer 20 on this laminate 15 and other interconnection layer 21 on the dielectric or less 20, a step of etching both layers 21, 20 to form vias 31 and a step of depositing a different interconnection layer 40 on the interconnect layer 21 and in the via holes 31. The layer 40 electrically couples the interconnection layers 15 and 21.</p> |
