| 摘要 |
An integrated circuit (IC) chip (200), mounted on a leadframe, has a network of power distribution lines (251,252) deposited on the surface of the chip so that these lines are located over active components (202,203) of the IC, connected vertically by metal-filled vias (260) to selected active components below the lines, and also by conductors (240,241) to segments of the leadframe. The network relocates most of the conventional power distribution interconnections from the circuit level to the surface network. The network is electrically connected to selected active components by metal-filled vias. The network relocates most of the bond pads dedicated to power supply from the conventional alignment along the chip periphery onto the newly created bondable lines. The network is deposited and patterned in wafer processing as a sequence of metal layers specifically suited for providing power current and electrical ground potential. The network has attachable outermost metal surface and is laid out so that network portions form pads convenient for attaching balls of bonding wires or solder. <IMAGE> |
