| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor-memory wiring structure which increases an operation speed and improves integration, and to improve the reliability of a memory chip by attaining a wiring structure which increases integration and reduces the chip size while sufficiently providing power. SOLUTION: A semiconductor memory has work lines (WL0 to WLn ) connected in strapping regions 501 to a gate layer of memory cells extended in a row direction. The end of the word lines WL are provided in the middle of a cell array region 303. On the other hand, power lines 100 and 110 for the same layer of that of the word lines are provided in a portion where no word line is provided, thus constructing a power-lien wiring structure. As the power lines, which are provided in a peripheral region in a conventional structure, are arranged in the memory cell array, the number of memory cells can be increased to increase the capacity, or the chip size can be reduced.</p> |
