发明名称 |
High speed lock acquisition mechanism with time parameterized cache coherency states |
摘要 |
A multiprocessor data processing system requires careful management to maintain cache coherency. In conventional systems using a MESI approach, two or more processors will often compete for ownership of a common cache line. As a result, ownership of the cache line will frequently "bounce" between multiple processors, which causes a significant reduction in cache efficiency. The preferred embodiment provides a modified MESI state which holds the status of the cache line static for a fixed period of time, which eliminates the bounce effect from contention between multiple processors.
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申请公布号 |
US6629212(B1) |
申请公布日期 |
2003.09.30 |
申请号 |
US19990437187 |
申请日期 |
1999.11.09 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ARIMILLI RAVI KUMAR;ARIMILLI LAKSHMINARAYANA BABA;DODSON JOHN STEVEN;GUTHRIE GUY LYNN;STARKE WILLIAM JOHN |
分类号 |
G06F12/08;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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