Flash memory array for multiple simultaneous operations

摘要

A non-volatile integrated circuit memory having an AND-like array structure that is capable of simultaneous reading and writing of digital data to multiple memory cells within the integrated circuit memory has memory cells within an array block of memory cells are arranged in columns and rows. A plurality of block bit lines is in communication with each array block of memory cells such that each block bit line interconnects the memory cells of one column of memory cells within one array block. A plurality of word lines is in communication with each array block of memory cells such that each word line interconnects the memory cells of one row within one array block. The integrated circuit memory further includes a plurality of global bit lines in communication with the array blocks to select a column of the array blocks and to transfer the digital data from and to the array blocks. A bit line selector selectively connects the plurality of global bit lines to the block bit lines. An array controller controls selection of a row of a block of the array, control transfer of the digital data from selected global bit lines to selected block bit lines, control transfer of the digital data to other selected global bit lines from other selected bit lines to allow simultaneous transfer of the digital data from and to selected memory cells.