| 摘要 |
In a phase detection circuit, an incoming data signal is fed to one D flip-flop which is enabled off of a rising or positive edge of the clock which in turn feeds its output to a second D flip-flop enabled off of the same clock edge. The same incoming data is also fed to a third D flip-flop which is enabled off of a falling or negative clock edge of the same clock signal. The output of which is in turn fed into a fourth D flip-flop which is enabled off of the same negative edge. The incoming data is also fed to a first XOR gate, along with the output of the first D flip-flop to generate the error phase detection signal. The outputs of the second and fourth D flip-flops are fed into a second XOR gate to generate the reference phase detection signal.
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