发明名称 Circuit, method and/or architecture for improving the performance of a serial communication link
摘要 A circuit comprising a plurality of communication devices each configured to receive and transmit one or more data packets in response to one or more control signals and a control circuit configured to generate the one or more control signals in response to the one or more data packets.
申请公布号 US6628656(B1) 申请公布日期 2003.09.30
申请号 US19990371051 申请日期 1999.08.09
申请人 CYPRESS SEMICONDUCTOR CORP. 发明人 RAZA S. BABAR
分类号 H04L12/56;(IPC1-7):H04J12/56 主分类号 H04L12/56
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