| 摘要 |
PROBLEM TO BE SOLVED: To provide a frequency multiplying circuit capable of sharply reducing the number of gates and reducing a circuit scale as a whole. SOLUTION: A frequency measuring counter 13 counts up clock signals of which frequency is halved by a frequency halving circuit 12 at the 'H' level period of an input signal. The count value of the counter 13 is set up in an output signal generating counter 14 as a frequency measured value. When the count value is set up, the counter 14 starts the counting operation of clock signals from a ring oscillation circuit 11, and every time that the count value coincides with the set value, outputs a signal indicating the coincidence. A flip flop 15 generates and outputs an output signal of which level is inverted in each rise of an output signal from the counter 14. Consequently the output signal of the flip flop 15 becomes twice the frequency of the input signal inputted to the counter 13. COPYRIGHT: (C)2003,JPO
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