发明名称 LAMINATED CHIP THERMISTOR AND METHOD OF CONTROLLING RESISTANCE VALUE OF THE SAME
摘要 PROBLEM TO BE SOLVED: To adjust the resistance value of a laminated chip thermistor by combining standardized electrode patterns with each other. SOLUTION: An elemental laminated chip thermistor body contains two or more laminated internal electrode layers. Each internal electrode is a combination of one or more main electrode sheets 1A (1B and 1C) and one or more adjusting electrode sheets 4 and the electrode sheets 1A (1B and 1C) and 4 have standardized electrode patterns formed in identical planes to face each other in paired states in the elemental chip thermistor body. The intervals d<SB>1</SB>between the paired main electrode patterns of the main electrode sheets 1A (1B and 1C) are made narrower than the intervals between the paired main electrode patterns d<SB>2</SB>of the adjusting electrode sheets 4. The resistance value of the laminated chip thermistor is adjusted to a target value by laminating the main electrode patterns upon each other and the adjusting electrode sheets 4 upon another. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003272903(A) 申请公布日期 2003.09.26
申请号 JP20020072323 申请日期 2002.03.15
申请人 OIZUMI SEISAKUSHO:KK 发明人 TANABE YOSHIHIRO;OKADA MASAHISA;TOYOKAWA KENICHI;NISHIMURA TOSHIAKI
分类号 H01C7/04;(IPC1-7):H01C7/04 主分类号 H01C7/04
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