| 摘要 |
PROBLEM TO BE SOLVED: To provide a data bus control device enabling reduction of variation in signal delay amount between bits in a data bus when devices different in bit width are connected to a common data bus. SOLUTION: In the data bus control device, an internal data bus of a CPU is divided into a high order 16-bit side and a low order 16-bit side, internal buffers 21, 22 are provided for holding the data of the high order 16-bit side, and internal buffers 23 to 26 are provided for holding the data of the low order 16-bit side. The external terminals 41, 42 connected to the data bus are provided with external buffers 31, 32 connected to the respective internal buffers 23 to 26 to hold the data of the high order 16-bit side, and external buffers 33, 34 for holding the data of the low order 16-bit side. When the CPU gains access to a peripheral device connected to the high order 16-bit side of the data bus, the state of each buffer is on-off controlled according to a bus control signal, to thereby replace the high order 16-bit side of the input/output data with the low order 16-bit side thereof. COPYRIGHT: (C)2003,JPO
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