| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an operation verification system that can verify a stable operation at device mounting, and an adaptive control system that can speed up arithmetic up to its internal stable operation limit and reduce loads on a control circuit within an internal stable operation range. <P>SOLUTION: The operation verification system is provided with: a normal operation circuit 104 that is constituted of a clock generation part 101 for generating an operation clock; a first memory element 102 as an operation verification target and an arithmetic circuit group 103; and an operation verification circuit 107 that is constituted of a second memory element 105 that stores the same data as stored in the first memory element 102 with a clock having a different phase, and a determination unit 106 for determining whether the normal operation circuit 104 is stably operated or not on the basis of outputs from the first and second memory elements 102 and 105, and monitors an output from the determination unit 106, to perform the verification of the high-speed operation of the first memory element 102 at a low operation frequency. <P>COPYRIGHT: (C)2003,JPO</p> |
