| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To read data at a high speed with an external clock signal being synchronized with a system clock signal, when data are read from a single-port memory in response to the external clock signal. <P>SOLUTION: An asynchronous read detecting section receives an external clock signal and detects odd-number-ths and even-number-ths read events. A synchronous timing generating section generates a first and a second control signals by the odd-number-ths and even-number-ths read events. A first and a second latch sections latch data from a single-port memory, and a third latch section latches odd-number-ths data. The first and the third latch sections latch, in response to the second control signal, and the second latch section latches in response to the first control signal. In response to a switchover signal, the odd-number-ths data from the third latch section and the even-number-ths data from the second latch section are selected as output data. <P>COPYRIGHT: (C)2003,JPO</p> |
