| 摘要 |
PROBLEM TO BE SOLVED: To improve verification efficiency by making it possible to find the cause easily and quickly when an error occurs. SOLUTION: In verifying the model of a logic circuit including a processor by simulating the logic circuit by means of a simulator, whenever a command is given to the processor and the processor execute the command, error detecting operation is made by monitoring the inside path of the processor (S1, S5, S7, S9, S11, S13, S15 and S17), and when an error is detected, the error is classified and the error code based on the classification is output, and a memory is dumped (S3) and a signal indicating abnormality is output (S3). The simulator responses to this signal and finishes the simulation. COPYRIGHT: (C)2003,JPO
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