| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method, especially a treatment method in a damascene process which relaxes stresses remaining in wirings or vias to reduce wiring defects, etc., due to formed voids. SOLUTION: In a damascene process which forms a wiring material such as Cu, W, etc., by plating in vias or wiring trenches formed in a layer insulation film through a barrier metal composed of a single layer film of Ti, TiN, Ta, TaN, WN, etc., or a laminate of two or more combined films thereof and anneals at high temperatures of 200-400°C to fill the vias or the wiring trenches with the wiring material by the CMP method, cooling is performed at a temperature of -75°C or lower before CMP after high temperature annealing, or at a temperature of -100°C or lower (preferably, -196°C or lower) after forming multilayer wiring. This configuration relaxes remaining tensile stresses in wirings or vias to avoid forming voids. COPYRIGHT: (C)2003,JPO
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