发明名称 CLOCK SIGNAL GENERATOR AND RECEIVER INCORPORATING THE SAME CLOCK SIGNAL GENERATOR
摘要 <p><P>PROBLEM TO BE SOLVED: To decode encoded data after detection without omission in the case of reception of digital modulation waves to which no preamble is imparted. <P>SOLUTION: The digital modulation waves after reception and detection are supplied to a memory circuit 8 as a storage means. The memory circuit 8 successively introduces digital signals and successively transmits them to a demodulation circuit 9 after storing them for over length of prescribed time T. While the prescribed time T elapses, a clock signal generation circuit 10 successively reads a plurality of the digital signals stored in the memory circuit 8 and reproduces clock signals synchronized with a signal cycle of transmitted encoded data. Consequently, decoding of received encoded data to be supplied to the decoding circuit 9 after the prescribed time T without omission is enabled and a practically excellent effect can be obtained by adopting the decoding to analysis of the received data, etc. <P>COPYRIGHT: (C)2003,JPO</p>
申请公布号 JP2003273943(A) 申请公布日期 2003.09.26
申请号 JP20020076880 申请日期 2002.03.19
申请人 TOSHIBA CORP 发明人 KANEKO ICHIRO
分类号 H04L27/00;H04L7/00;(IPC1-7):H04L27/00 主分类号 H04L27/00
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