发明名称 Voltage change reflecting delay calculation method, and voltage change reflecting delay calculation system
摘要 A method for designing a semiconductor integrated circuit is proposed. The semiconductor integrated circuit includes power supply terminals each formed out of an area bump and signal terminals. Distance from the logic cell or the module to a power supply area bump closest thereto is obtained for the logic cell or the module. Further, a power supply voltage which is estimated to be actually applied to the logic cell or the module is obtained based on the obtained distance and a power supply voltage applied to the power supply area bump. Finally, a delay is calculated based on the estimated power supply voltage.
申请公布号 US2003182637(A1) 申请公布日期 2003.09.25
申请号 US20030345989 申请日期 2003.01.17
申请人 FUJITSU LIMITED 发明人 KUROSE SHINICHI;GOTO SEIJI
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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