发明名称 Data retaining circuit
摘要 A data retaining circuit has been disclosed in which, even if a soft error occurs, it is corrected and a normal value can be maintained, the configuration is simple, and high-speed operations are enabled. In this circuit, when a soft error occurs in the data to be put out, it is corrected by a pull-up path or a pull-down path, and when a soft error occurs in the data in the pull-up path or the pull-down path, the error data in the pull-up path or the pull-down path is prevented from affecting each other, as well as turning off the correcting function to prevent the influence on the data to be put out.
申请公布号 US2003179031(A1) 申请公布日期 2003.09.25
申请号 US20020282862 申请日期 2002.10.28
申请人 ARIMA YUKIO;YAMASHITA TAKAHIRO;ISHIBASHI KOICHIRO 发明人 ARIMA YUKIO;YAMASHITA TAKAHIRO;ISHIBASHI KOICHIRO
分类号 G11C11/417;H03K3/037;H03K3/356;H03K3/3565;H03K17/16;H03K19/003;H03K19/0175;(IPC1-7):H03K3/037 主分类号 G11C11/417
代理机构 代理人
主权项
地址