发明名称 Distributed 4-bits diagonal interleaved parity ( DIP4) checker
摘要 A logic circuit includes an interface and an error detection unit. The interface is configured to receive and transmit a data stream, wherein the data stream includes at least one of a variable length burst and a fixed length burst. The error detection unit is configured to detect an error detection code when a misalignment occurs within the data stream by calculating recursive terms.
申请公布号 US2003182613(A1) 申请公布日期 2003.09.25
申请号 US20020234165 申请日期 2002.09.05
申请人 BROADCOM CORPORATION 发明人 CHU NGOK YING
分类号 G06F11/10;H03M13/00;H03M13/33;H04L1/00;(IPC1-7):H03M13/00 主分类号 G06F11/10
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