发明名称 METHOD AND APPARATUS FOR SYNTHESIS
摘要 Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure base don the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (49 replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions. In some embodiments, this method is performed to map a design to a particular technology library. Some embodiments provide a data storage structure that stores a plurality of sub-networks based on parameters derived from the output functions of the sub-networks.
申请公布号 WO03077630(A2) 申请公布日期 2003.09.25
申请号 WO2003US02984 申请日期 2003.01.31
申请人 CADENCE DESIGN SYSTEMS, INC.;TEIG, STEVEN;ASMUS, HETZEL 发明人 TEIG, STEVEN;ASMUS, HETZEL
分类号 G06F17/50;G06F9/455 主分类号 G06F17/50
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