发明名称 |
Fabrication process of a trench gate power MOS transistor with scaled channel |
摘要 |
A process for forming a trench gate power MOS transistor includes forming an epitaxial layer having a first type of conductivity on a semiconductor substrate, and forming a body region having a second type of conductivity on the epitaxial layer. A gate trench is formed in the body region and in the epitaxial layer. The process further includes countersinking upper portions of the gate trench, and forming a gate dielectric layer on surfaces of the gate trench including the upper portions thereof. A gate conducting layer is formed on surfaces of the gate dielectric layer for defining a gate electrode. The gate conducting layer has a thickness that is insufficient for completely filling the gate trench so that a residual cavity remains therein. The residual cavity is filled with a filler layer. The gate conducting layer is removed from an upper surface of the body region while using the filler layer as a self-aligned mask. The edge surfaces of the gate conducting layer are oxidized. Source regions are formed by implanting dopants in the body region while using the oxidized edge surfaces as a self-aligned mask, and the implanted dopants are diffused in the body region.
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申请公布号 |
US2003181011(A1) |
申请公布日期 |
2003.09.25 |
申请号 |
US20030351281 |
申请日期 |
2003.01.24 |
申请人 |
STMICROELECTRONICS S.R.I. |
发明人 |
CURRO GIUSEPPE;FAZIO BARBARA |
分类号 |
H01L21/336;H01L29/49;H01L29/78;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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