CMOS DIGITAL PULSE WIDTH MODULATION CONTROLLER

摘要

A CMOS digital PWM controller chip (10) includes a clock generator (14) for directly generating a sampling clock at a frequency higher than a control pulse rate without requiring a phase locked loop, an oversampling analog-to-digital converter (24) clocked by the sampling clock for converting error signals into filtered digital values, an output for controlling duty cycle of an electrical device in accordance with width-modulated digital control pulses supplied at the control pulse rate, and, digital control logic for generating the width-modulated digital control pulses in relation to the digital values. The digital control logic may include a linear feedback shift register to pseudo-randomize the digital control pulses to reduce electromagnetic interference.