发明名称 |
Block redundancy implementation in heirarchical RAM's |
摘要 |
The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.
|
申请公布号 |
US2003179641(A1) |
申请公布日期 |
2003.09.25 |
申请号 |
US20020176843 |
申请日期 |
2002.06.21 |
申请人 |
TERZIOGLU ESIN;WINOGRAD GIL I.;AFGHAHI CYRUS |
发明人 |
TERZIOGLU ESIN;WINOGRAD GIL I.;AFGHAHI CYRUS |
分类号 |
G06F13/40;G11C7/06;G11C7/18;G11C11/419;G11C29/00;(IPC1-7):G11C8/00 |
主分类号 |
G06F13/40 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|