发明名称 |
SHARED PROGRAM MEMORY WITH FETCH AND PREFETCH BUFFERS |
摘要 |
Multiple processors are connected to a single program store memory. Access t o the program memory is controlled by an arbiter. There is a wide interface to the memory and local storage to reduce latency due to multiple processors attempting to access the memory simultaneously. There is also prefetch circuitry to further reduce this latency.
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申请公布号 |
CA2378777(A1) |
申请公布日期 |
2003.09.25 |
申请号 |
CA20022378777 |
申请日期 |
2002.03.25 |
申请人 |
CATENA NETWORKS CANADA INC. |
发明人 |
MES, IAN |
分类号 |
G06F9/38;G06F12/00;G06F13/16;G06F15/167;(IPC1-7):G06F13/16 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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