| 摘要 |
A processor apparatus which reduces an overhead at the time of switching processing modules and efficiently performs desired processing at a high speed, wherein desired processing is performed by prefetching a series of instructions by a main program prefetcher, pre-decoding the same by a pre-decoder, and supplying the same to a decoder and execution unit via a multiplexer. When an instruction to execute a macro command is detected in the pre-decoder, the instructions of the macro command are prefetched by a macro program prefetcher and pre-decoded in the pre-decoder. As a result, when branching to a macro command, the instructions of the macro command can be immediately supplied to an execution unit only by switching the multiplexer.
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