| 摘要 |
<p>An information processing apparatus capable of performing memory access from a plurality of processors without crashing the memory access. The information processing apparatus (101) includes a pre-stage processor (3) for adjusting a plurality of access requests to an integral memory (5) by an access request control circuit (22) and issuing a predetermined number of access requests, a post-stage processor (4) for issuing a plurality of access requests to the integral memory (5), and an integral memory control circuit (18) for adjusting access requests from the pre-state processor and the post-stage processor and outputting one of the access requests. The access request control circuit (22) and the integral memory control circuit (18) are adjusted according to the periodicity of each access factor and the regularity of the access destination.</p> |
