发明名称 |
Display device |
摘要 |
The present invention realizes a display device having C-MOS p-Si TFTs which enable the high integration by reducing spaces for P-MOS TFTs and N-MOS TFTs in driving circuit or the like thereof. The present invention adopts a self-aligned C-MOS process which uses a half tone mask as an exposure mask for manufacturing the C-MOS p-Si TFTs mounted on the display device. With the use of the half tone mask, the alignment or positioning at a bonding portion between a P-MOS portion and an N-MOS portion becomes unnecessary and hence, the number of photolithography steps can be reduced and the high integration of C-MOS TFT circuits can be realized. |
申请公布号 |
US2003178650(A1) |
申请公布日期 |
2003.09.25 |
申请号 |
US20030392862 |
申请日期 |
2003.03.21 |
申请人 |
SONODA DAISUKE;KANEKO TOSHIKI |
发明人 |
SONODA DAISUKE;KANEKO TOSHIKI |
分类号 |
G02F1/1368;G02F1/1362;H01L21/336;H01L21/77;H01L21/8238;H01L21/84;H01L27/08;H01L27/092;H01L27/12;H01L27/32;H01L29/786;(IPC1-7):H01L27/10 |
主分类号 |
G02F1/1368 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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