| 摘要 |
A method of handling instructions in a load/store unit of a processor by dispatching instructions to the load/store unit, filling all physical entries of a reorder queue with tags corresponding to the instructions, and further dispatching one or more additional instructions to the load/store unit while all of the physical entries in the reorder queue are still full, i.e., still contain tags for uncompleted instructions. The invention may be implemented in either a load reorder queue or a store reorder queue. Multiple logical instruction tags are assigned in a count greater than the number of physical entries in the reorder queue. Of the multiple logical instruction tags assigned to a single one of the physical entries in the reorder queue, only the tag for the oldest instruction is allowed to execute. At least one virtual bit (VT) is provided to tag allocations for the load/store unit. This VT bit is flipped when a corresponding tag allocation wraps. The most significant bit of a given logical instruction tag is compared with the VT bit to determine whether the given logical instruction tag is valid, i.e., is actually stored in a physical entry of the reorder queue.
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