发明名称 DELAY TIME ADJUSTING CIRCUIT AND WIRING METHOD USING IT
摘要 PROBLEM TO BE SOLVED: To provide simple delay time adjustment for layout design in a step of designing the layout of a semiconductor integrated circuit. SOLUTION: The target delay time adjustment is achieved without performing any wiring correction in a block by presetting a plurality of wiring routes having different lengths in the block and switching the routes by using switching cells.
申请公布号 JP2002203906(A) 申请公布日期 2002.07.19
申请号 JP20000402357 申请日期 2000.12.28
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 OZAWA SHIGEO;KIMURA FUMIHIRO;FUJII TSUTOMU
分类号 H01L27/04;H01L21/82;H01L21/822;(IPC1-7):H01L21/82 主分类号 H01L27/04
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