| 摘要 |
<p>A Fast Hadamard Transform device is provided which transforms n elements of input data (V1-V8), each composed of p bits using n shift register units (201-208). Additionally the transformer comprises n/2 butterfly computation units (211-214). Each of the shift registers inputs a data signal in response to a clock signal and then data stored in the shift register units are supplied to the outputs (W1-W8) as quantized data by providing a signal for each log2n*(p+log2n) clock pulse. <IMAGE></p> |
