发明名称 |
Multiple logical bits per memory cell in a memory device |
摘要 |
A read-only memory device is described having non-volatile memory cells that include a memory component connected between electrically conductive traces. A memory component is formed to include a resistor that indicates a resistance value when a potential is applied to a selected memory cell. The resistance value of a memory component in an individual memory cell corresponds to multiple logical bits. The resistance value of a memory component corresponding to a set of logical bits can be based on a thickness and/or an area of electrically resistive material that forms the memory component, and/or based on the geometric shape of the memory component, where different geometric shapes of the electrically resistive material have different resistance values that correspond to different sets of logical bits.
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申请公布号 |
US6625055(B1) |
申请公布日期 |
2003.09.23 |
申请号 |
US20020120113 |
申请日期 |
2002.04.09 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
SMITH KENNETH K.;BRANDENBERGER SARAH M.;BLOOMQUIST DARREL R.;ELDREDGE KENNETH J.;VAN BROCKLIN ANDREW L.;FRICKE PETER J. |
分类号 |
G11C11/56;(IPC1-7):G11C11/00 |
主分类号 |
G11C11/56 |
代理机构 |
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主权项 |
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地址 |
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