发明名称 |
Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions |
摘要 |
The manufacturing method comprises, in sequence, the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a layer of silicide on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining stack gate regions and HV gate regions of high-voltage transistors; and forming HV source and drain regions and cell regions. |
申请公布号 |
US6624015(B2) |
申请公布日期 |
2003.09.23 |
申请号 |
US20010010049 |
申请日期 |
2001.11.09 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
PATELMO MATTEO;DALLA LIBERA GIOVANNA;GALBIATI NADIA;VAJANA BRUNO |
分类号 |
H01L21/8247;H01L27/10;H01L27/105;H01L27/115;H01L29/423;H01L29/788;H01L29/792;(IPC1-7):H01L21/823 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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