| 摘要 |
A methodology for translating multiple bit conditional expressions of a non-Verilog hardware description language (HDL) program, not readily recognized by Verilog HDL, which can then be used to realize a logic circuit design embodied by the non-Verilog HDL program. Conditional IF expressions occurring within the HDL program that are not recognized by Verilog HDL are processed so that they can be accordingly translated to Verilog HDL syntax. If the conditional IF expression is a multiple-bit expression, a binary operator statement having bit-wise binary operators, including two AND operators, one OR operator, and one NOT operator, that is equivalent to the conditional IF expression is created. If either the THEN expr1 and/or the ELSE expr2 expressions are themselves multiple-bit expressions nested within the main multi-bit IF expression, then the nested multiple-bit expressions expr1 and/or expr2 in the binary operator statement must be replaced by the appropriate incremental variable(s) to create an always statement that can be translated to generate a Verilog HDL statement that is equivalent to the conditional expression. The nested multiple-bit expressions expr1 and/or expr2 are represented within the always statement by one or more corresponding incremental variables. Synthesis can then be performed on the always statement or on the binary operator statement, if there are no nested multiple-bit conditional expression, by a processor of a logic synthesis tool to generate a logic circuit representative of the non-Verilog HDL program.
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