发明名称 ATM-cell segmentation and reassembly circuit
摘要 An ATM-cell segmentation and reassembly circuit, wherein BUS packets can be relayed at high speed without dissipating memory resources, includes a receiving-cell processing unit (100) for reassembling received cells into received packets, a transmission-cell processing unit (200) for segmenting transmission packets into transmission cells, a packet memory (300) for storing the received packets and the transmission packets, and a descriptor section (104) shared by the received-cell processing unit (100) and the transmission-cell processing unit (200) for registering reception descriptors to be used for reassembling the received cells and transmission descriptors to be used for segmenting the transmission packets, wherein a reception descriptor used for reassembling the received cells into a received packet is used as a transmission descriptor for segmenting the received packet into the transmission cells when the received packet is to be relayed towards another terminal.
申请公布号 US6625123(B1) 申请公布日期 2003.09.23
申请号 US19990310864 申请日期 1999.05.13
申请人 NEC CORPORATION 发明人 FUKUMOTO KEISUKE;HATTORI YUKO
分类号 H04Q3/00;H04L12/56;H04Q11/04;(IPC1-7):H04L12/56 主分类号 H04Q3/00
代理机构 代理人
主权项
地址