Fast A/D conversion signal processor, RF receiver circuit, digital receiver front end circuit, MRI apparatus, and fast A/D conversion device

摘要

For the proper delivery of digital data D_AD from a fast A/D converter to a digital signal process section, the digital data is stored in a dual-clock-synchronous FIFO by being timed to the output of digital data from the fast A/D converter (at the timing based on a data ready signal DATA_RDY). The dual-clock-synchronous FIFO reads out digital data D_FIFO and delivers to the digital signal process section by being timed to the operation of the digital signal process section (at the timing based on a clock signal CLK_DIG for a digital signal process).