SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND DIGITAL CAMERA SYSTEM

摘要

PROBLEM TO BE SOLVED: To prevent pseudo lock and to generate a clock the delay time of which is adjusted with high precision.

SOLUTION: A pulse width fixing divider 2 generates a divider output clock from a fundamental clock. In the divider output clock, one cycle of the fundamental clock among eight cycles of the fundamental clock becomes a Hi signal and periods of other seven cycles become Lo signals. A delay circuit 3 outputs a delayed clock formed by delaying the divider output clock by one cycle of the fundamental clock and an inverter 7 outputs a divider output inverted clock by inverting the divider output clock. A phase comparator 4 generates UP/ DOWN pulses from the phase difference between the delayed clock and the divider output inverted clock. A charge pump 5 and a loop filter 6 generate a control voltage CNTL by the UP/DOWN pulses and perform control so that the delay clock becomes a locked state in one cycle of the fundamental clock.

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