| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To improve timing resolution of a memory regardless of a bus clock frequency. <P>SOLUTION: This memory system is equipped with a main memory 17 and a memory control device 16. The main memory 17 is equipped with one or more blocks having a plurality of banks. The memory control device 16 is equipped with a plurality of data channels, and each data channel can access one or more banks in the main memory 17. Each data channel is equipped with write FIFO buffers 145, 147 for supporting efficiently a cache purge operation and a normal write operation, and reflection type write FIFO buffers 146, 148 for supporting efficiently a simultaneous cache copy back operation and coherent read. <P>COPYRIGHT: (C)2003,JPO</p> |
