| 摘要 |
<p>A high fan-out hub array system (20) and method is provided. The system (20) includes at least one hub (HUB0-HUB4) that contains user logic that receive signals from various chips (1565-1580) and boards (1551-1556), and which quickly turnarounds another signal (based on logic) out to the desired chips (1565-1580) and boards (1551-1556). In a CLKGEN (2871) implementation, a global clock is generated in the hub (HUB0-HUB4) and distributed in a high fan-out manner to all the FPGA logic chips (1565-1580) in the system (20). For a bus resolution application, a hub (HUB0-HUB4) contains bus resolution logic to resolve bus access requests. It resolves the various requests and delivers the result to all the relevant chips (1565-1580) and boards (1551-1556). In a STOPWHEN application, when a STOPWHEN condition has been met, the system delivers a pause signal to all the chips (1565-1580) and boards (1551-1556) via the high fan-out hubs (HUB0-HUB4).</p> |
