| 摘要 |
A microcomputer capable of efficiently accessing a plurality of devices with different access speeds through a shared bus. If, during access to a first device in compliance with a first access request, a second access request for a second device is issued from a CPU, an access completion time determination section determines the relation of order in time between the completion time of the access to the first device and the earliest time at which the access to the second device can be completed. If it is judged by the access completion time determination section that the access to the second device can be completed earlier than the completion time of the access to the first device, a bus access section accesses the second device in compliance with the second access request during the processing cycle of the access to the first device in compliance with the first access request.
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