| 摘要 |
An Automatic Frequency Control (AFC) circuit for a mobile terminal employs a fractional-N Phase Locked Loop (PLL) to directly reduce errors in the synthesized frequency, such as due to component tolerances, temperature drift, and the like. The frequency error is detected by the average speed of rotation of the I,Q constellation. A corresponding offset is added to the tuning frequency selection word prior to encoding, such as in a DELTASIGMA modulator, to generate an effective non-integer PLL frequency division factor over a specified duration. The DELTASIGMA modulator may include dithering the different integer values by a pseudo-random number to minimize noise in the output frequency spectrum introduced by the fractional-N division. Component and parameter selection allow a high degree of resolution in frequency control of the fractional-N PLL. By directly controlling for the frequency error, a DAC and XTAL oscillator tuning circuit may be eliminated from the AFC circuit.
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