| 摘要 |
There is disclosed a field programmable gate array (FPGA) that performs bit swapping functions in the interconnects rather than in the configurable logic blocks of the FPGA. The FPGA comprises: 1) a plurality of configurable logic blocks, including a first CLB having an N-bit output and a second CLB having an N-bit input; 2) a plurality of interconnects; 3) a plurality of interconnect switches for coupling ones of the plurality of interconnects to each other and to inputs and outputs of the plurality of configurable logic blocks; and 4) an interconnect switch controller for controlling the plurality of interconnect switches, wherein the interconnect switch controller in a first switch configuration causes a first group of interconnects coupled to the N-bit output of the first CLB to be coupled to a second group of interconnects coupled to the N-bit input of the second CLB according to a first connection mapping and wherein the interconnect switch controller in a second switch configuration causes the first group of interconnects to be coupled to the second group of interconnects according to a second connection mapping.
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