| 摘要 |
An integrated circuit to which a metal multi-layered wiring technique is applied is structured on a semiconductor substrate 11. There is a metal wiring layer immediately below an interlayer dielectric film 121. A capacitor element C1, which is formed from a specified wiring layer metal 13 on the interlayer dielectric film 121, a capacitor dielectric film 14 in a specified region on the wiring layer metal 13 and a metal pattern 15 thereon, is provided. Further, on the next interlayer dielectric film 122, lead-out electrodes T13 and T15 as parts of the capacitor element C1, which are lead out through vias VIA formed from, for example, W plugs, are formed with a wiring layer metal 16 in an upper layer.
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