| 摘要 |
A DLL circuit generates first and second internal clocks delayed by appropriate quantities from an external clock, and generates third and fourth internal clocks capable of driving a data output circuit after a CAS latency from the first and second internal clocks on the basis of an internal signal. A repeater recovers signal levels of the third and fourth internal clocks and outputs the third and fourth internal clocks as DLL clocks. The data output circuit takes in read data using the DLL clocks outputted from the repeater, and outputs the read data to an outside in a half cycle synchronously with the DLL clocks. In this way, a circuit area of a semiconductor memory device can be reduced by generating the DLL clocks in a prior stage to the data output circuit.
|
