| 摘要 |
A semiconductor memory device includes a memory cell which has a transistor and a ferroelectric capacitor, the transistor having a source-drain path and a gate connected to a word line, the capacitor being connected at a first end to a plate line and connected at a second end to a bit line through the source-drain path. A control circuit controls, during a test-mode operation, the memory cell so that a plate-line signal sent through the plate line to the memory cell and a bit-line signal sent through the bit line to the memory cell are set at a same potential.
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