| 摘要 |
Disclosed is a data output driver which improves the timing margin of a memory operation by reducing skew related to data output in a semiconductor memory device. A register receives and stores a plurality of first parallel data in synchronization with clock signal and outputs a plurality of second parallel data. A controller compares a plurality of parallel data currently inputted to register with a plurality of parallel data previously inputted to register in response to delayed clock signal, and calculates the number of data transitions based on the comparison result, and generates a control signal according to calculated number of data transitions. A clock signal delay part delays clock signal according to a logic level of control signal in order to generate a pair of corrected clock signals. A data selecting part selectively outputs odd or even numbered data among the plurality of second parallel data. An output driving part buffers and outputs output data of the data selecting part.
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